Resistive memory is a new class of non-volatile memory, which can retain the stored information when powered off. A resistive memory device normally comprises an array of memory cells, each of which includes at least a resistive memory element and a selection element coupled in series between appropriate electrodes. Upon application of an appropriate voltage or current to the resistive memory element, the electrical resistance of the resistive memory element would change accordingly, thereby switching the stored logic in the respective memory cell.
A resistive memory element can be classified into at least one of several known groups based on its resistively switching mechanism. The resistive memory element of Phase Change Random Access Memory (PCRAM) may comprise a phase change chalcogenide compound, which can switch between a resistive amorphous phase and a conductive crystalline phase. The resistive memory element of Conductive Bridging Random Access Memory (CBRAM) relies on the statistical bridging of metal rich precipitates therein for its switching mechanism. The resistive memory element of CBRAM normally comprises a nominally insulating metal oxide material, which can switch to a lower electrical resistance state as the metal rich precipitates grow and link to form conductive paths upon application of an appropriate voltage. The resistive memory element of Magnetoresistive Random Access Memory (MRAM) typically comprises at least two layers of different ferromagnetic materials with a non-magnetic spacer layer interposed therebetween. When a switching pulse is applied to the memory element of a MRAM device, one of the ferromagnetic layers will switch its magnetic field polarity, thereby changing the element's electrical resistance.
A selection element in a memory cell functions like a switch to direct current through the selected memory element coupled thereto. One common selection element is diode, which can reverse bias a non-selected memory cell. While a selection diode has a simple structure that can minimize the cell size of the resistive memory cell, a memory architecture employing the selection diode normally has a slower random access time. Another commonly used selection element is transistor, particularly Field Effect Transistor (FET), which allows for faster selection of memory cells and therefore faster random access time.
Field Effect Transistor (FET), particularly Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFET), is the fundamental building block of integrated circuits and is ubiquitous in modern electronic devices. In a MOSFET device, when an appropriate voltage is applied to a gate, charge carriers move between a source region and a drain region through a conductive channel, which is formed by an electric field generated by the gate voltage through a thin layer of dielectric material know as gate dielectric layer interposed between the gate and the channel.
FIG. 1A is a top view of an array of conventional selection transistors formed in a semiconductor substrate for a memory device. FIG. 1B is a top view of the same array of transistors with selection gates 94A-94D, isolation gate 96, and source lines 98A, 98B omitted to clearly illustrate structures therebeneath. Referring to FIG. 1B, the array of conventional transistors formed on a semiconductor substrate comprise a plurality of transistors 100, each of the transistors 100 (individually illustrated as transistors 100A-100H) comprises a respective drain 102A, 102B, 102C, 102D, 102E, 102F, 102G, or 102H (collectively represented as drains 102), a respective common source 104A, 104C, 104E, or 104G (collectively represented as sources 104) which is shared with an adjacent transistor, and a respective channel 106A, 106B, 106C, 106D, 106E, 106F, 106G, or 106H (collectively represented as channels 106) juxtaposed therebetween. As mentioned afore, each of the sources 104 is shared by two adjacent transistors, that is the transistors 100A and 100B share the source 104A, the transistors 100C and 100D share the source 104C, and so on. A plurality of isolation channels 108 are juxtaposed between the drains 102 to electrically isolate two adjacent transistors. Rows of transistors 100 are electrically isolated by Shallow Trench Isolation (STI) 110. Referring now to FIG. 1A, a plurality of parallel selection gates 94 are disposed on top of the channels 106 with a thin layer of gate dielectric (not shown) interposed therebetween. Each of the selection gates 94 is shared by multiple transistors along the extension direction thereof, that is the transistors 100A and 100E share the selection gate 94A, the transistors 100B and 100F share the selection gate 94B, and so on. Each of a plurality of parallel source lines 98A and 98B is coupled to a series of common sources 104 along the extension axis thereof. An isolation gates 96 is disposed on top of isolation channels 108 with a thin layer of gate oxide (not shown) interposed therebetween. Memory elements (not shown) are typically coupled to the drains 102 of the selection transistors 100. A memory cell or a bit includes a respective memory element and a selection transistor coupled thereto.
To be cost competitive, a small memory cell size is desired in order to increase device density. One way to achieve this is to simply shrink the feature size, F, which is the minimum resolvable photolithographic dimension in a particular process technology However, several difficulties can arise when scaling the size of the conventional transistors 100 illustrated in FIGS. 1A and 1B, particularly their channel width, W, to a few tens of nanometers. As the channel width is reduced, the current-carrying capacity or current drivability of the channel is correspondingly reduced. This is a significant issue for resistive memory devices, which require higher currents to switch their memory state.